1. Field of the Invention
The present invention relates to a decoder, and particularly relates to a decoder used for graphic processing or the like.
2. Description of the Related Art
In a digital circuit for performing graphic processing or the like, there is a case which requires a decoder supplied with coordinates of two points to decode an output signal expressing the relationship between the two points. An example thereof will be described with reference to FIG. 2.
In FIG. 2, reference numeral 20 represents a window of one dot in X- and Y-coordinate axes. The solid lines show borders per one dot, and the dotted lines show borders per 0.5 dot. The window 20 is constituted by four areas A, B, C and D separated by the borders per 0.5 dot, and the respective areas A, B, C and D are sets of points respectively satisfying the conditions of EQU {P.sub.a (x.sub.a,y.sub.a).vertline.0.ltoreq.x.sub.a &lt;0.5, 0.5.ltoreq.y.sub.a &lt;1.0}, EQU {P.sub.b (x.sub.b,y.sub.b).vertline.0.5.ltoreq.x.sub.b &lt;1.0, 0.5.ltoreq.y.sub.b &lt;1.0}, EQU {P.sub.c (x.sub.c,y.sub.c).vertline.0.ltoreq.x.sub.c &lt;0.5, 0.ltoreq.y.sub.c &lt;0.5}, and EQU {P.sub.d (x.sub.d,y.sub.d).vertline.0.5.ltoreq.x.sub.d &lt;1.0, 0.ltoreq.y.sub.d &lt;0.5}.
Now, it is assumed that two points P.sub.i and P.sub.j supplied into a decoder are both in {(x,y).vertline.0.ltoreq.x&lt;1.0, 0.ltoreq.y&lt;1.0} within the window 20, and that the two points are respectively within two of the four areas A, B, C and D which are diagonal to each other. That is, EQU (P.sub.i,P.sub.j).fwdarw.{(A,D),(D,A),(B,C),(C,B)}, (in which (P.sub.i,P.sub.j).fwdarw.(A,D)
expresses that the point P.sub.i belongs to the area A and the point P.sub.j belongs to the area D). The decoder outputs a signal uplow which shows whether the straight line connecting the points P.sub.i and P.sub.j exists above a center point of the window 20 (including the case where the straight line passes through the center point) or below the center point. Conventionally, this decoder is constituted in accordance by a method in which all the combinations of the coordinates of two points supplied thereto are decoded as they are. A circuit configuration using this method will be described more in detail.
Now, it is assumed that the coordinates of the two inputted points P.sub.i and P.sub.j are expressed with the accuracy of three bits down to the decimal place. In FIG. 2, the window 20 divided into four areas is divided into 64 lattice points by coordinates having values of three bits down to the decimal place so that 16 lattice points are included in each of the areas A to D. The sets of 16 lattice points included in each of the areas A, B, C and D are named A0 to A15, B0 to B15, C0 to C15, and D0 to D15, as shown in FIG. 3.
In order to obtain a signal uplow, it is necessary to decode all the combinations of the two points for the straight lines P.sub.i P.sub.j passing above the lattice point B0 for the every case of (P.sub.i,P.sub.j).fwdarw.{(C,B),(B,C),(A,D),(D,A)}. For example, in the case of (P.sub.i,P.sub.j).fwdarw.(C,B), the combinations making the signal uplow active are as follows.
TABLE 1 ______________________________________ P.sub.i P.sub.j ______________________________________ C0 B0,B4,B5,B8,B9,B10,B12,B13,B14,B15 C1 B0,B4,B8,B9,B12,B13,B14 C2 B0,B4,B8,B9,B12,B13 C3 B0,B4,B8,B12 C4 B0,B4,B5,B8,B9,B10,B12,B13,B14,B15 C5 B0,B4,B5,B8,B9,B10,B12,B13,B14,B15 C6 B0,B4,B8,B9,B12,B13,B14 C7 B0,B4,B8,B12,B13 C8 B0,B4,B5,B6,B8,B9,B10,B11,B12,B13,B14,B15 C9 B0,B4,B5,B8,B9,B10,B11,B12,B13,B14,B15 C10 B0,B4,B5,B8,B9,B10,B12,B13,B14,B15 C11 B0,B4,B8,B9,B12,B13 C12 B0,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15 C13 B0,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15 C14 B0,B4,B5,B6,B8,B9,B10,B11,B12,B13,B14,B15 C15 B0,B4,B5,B8,B9,B10,B12,B13,B14,B15 ______________________________________
A signal-uplow decoder may be constituted by decoding and logical OR circuits, in which the decoding circuit output signals expressing the correspondence between the inputted coordinates P.sub.i and P.sub.j and the foregoing combinations. Therefore, a conventional decoder for the signal uplow has such a circuit configuration as shown in FIG. 4, so that a logical OR circuit 25 outputs a signal level which takes a value of UPLOW=1 if the straight line P.sub.i P.sub.j passes on or above the lattice point B0, while takes a value of UPLOW=0 if it passes below the lattice point B0.
In FIG. 4, the decoder comprises a first decoding circuit 21, a second decoding circuit 22, a third decoding circuit 23, a fourth decoding circuit 24, and the above-mentioned logical OR circuit 25. The first to fourth decoding circuits 21 to 24 are for decoding the combinations of coordinates corresponding to (P.sub.i,P.sub.j).fwdarw.{(C,B),(B,C),(A,D), (D,A)} respectively, and each of the decoding circuits 21 to 24 is supplied with a 3-bit signal expressing the coordinates of the point P.sub.i and another 3-bit signal expressing the coordinates of the point P.sub.j. Each of decoding circuits 21 to 24 outputs a signal for every combination of coordinates which makes the signal uplow active. The logical OR circuit 25 performs logical ORing among all the outputs of the first to fourth decoding circuits 21 to 24 to thereby output the signal uplow.
However, in such a method of decoding combinations of coordinates of two inputted points as they are, the number of the combinations of coordinates is so large that a number of decoding circuits (four in this conventional example) is required. Thus, there is a problem that the scale of the circuit is so large that the speed of operating is low, and the cost is high.